1. Field of the Invention
The present invention relates to data processing systems, and particularly to a structured control instruction fetch unit that feeds structured control program instructions to a processor for execution.
2. Description of the Related Art
The problem of accessing instructions that are stored in a data store, such as memory, and providing them to a data processor has been addressed in a variety of ways. Dedicated local memory is fast, can provide a high bandwidth, is power efficient and readily available, but is costly in area. By contrast, on-die shared and/or arbitrated memory consumes more power and may not always be available or satisfy peak bandwidth requirements, but the cost of implementation is reduced. Off-chip memory is the cheapest, but suffers the largest penalty in power consumption, access latency and available bandwidth. Any limitation in memory access performance, either due to latency or bandwidth limitations, also inflicts a penalty in processor efficiency, as the processor will stall when the required instruction is not available. With respect to shared memory access, latency, bandwidth, and power consumption can be mitigated by providing an intermediate data store. In some systems, a program instruction cache is provided such that the instructions can be accessed from within the cache. This provides fast access of the instructions, but has the disadvantage of being a reactive mechanism, which makes autonomous decisions on which instruction to store based solely on the history of the instructions or instruction addresses being requested by the processor. To mitigate this disadvantage, caches are often equipped with complex prediction logic with the goal of maximizing the probability of keeping the requested instructions in its local store. As a consequence, such cache devices are very power hungry. This can be a particular disadvantage for lengthy programs having many stored instructions.
An alternative is to buffer the instructions prior to use in a FIFO buffer. This is cheaper than a cache, but has less flexibility. This lack of flexibility means that instructions have to be moved more often, which costs power and can also lead to stalling in the processor when an instruction is not available at the appropriate time.
Many of the above solutions are specific to particular architectures, so that a new architecture needs to be designed.
Thus, a structured control instruction fetch unit solving the aforementioned problems is desired.